1. Technical Field
Embodiments of the present invention relates to an apparatus and method of generating a data bus inversion (DBI) signal in a semiconductor integrated circuit, and more particularly, to an apparatus and method of generating a DBI signal in a semiconductor integrated circuit that increases an area margin.
2. Related Art
In general, semiconductor integrated circuits, such as semiconductor memory apparatuses, output data in multiples of 2 (for example, 128 and 256 data). To this end, the semiconductor integrated circuit includes many data output buffers, and drives data transmitted through global lines. Each of the data output buffers includes an MOS transistor. Each of the MOS transistors drives the data according to the level of each of the data and outputs the driven data to the outside of a chip.
The state of each of the MOS transistors constituting the data output buffers is determined according to a logic value of the data. For example, when data at a high level is transmitted to the data output buffer, which is composed of an NMOS transistor, the NMOS transistor is turned on, such that current flows between a drain terminal and a source terminal of the NMOS transistor. As the number of MOS transistors increases, the current that flows among the plurality of MOS transistors included in the plurality of data output buffers increases, the semiconductor integrated circuit has a high current loss, and thus, power efficiency is reduced.
In order to solve the above-described current loss, a data bus inversion (DBI) technique is introduced into the semiconductor integrated circuit according to the related art. According to the DBI technique, it is determined how many data generate current for transistors of data output buffers among a predetermined number of data (for example, 8 data). When it is determined that a lot of data generates current, the data is inverted to thereby reduce the current loss. For example, when NMOS transistors are included in data output buffers, the semiconductor integrated circuit does not invert the data when among the eight data, less than 5 data are at a high level, but transmits the data to the data output buffers. On the other hand, the semiconductor integrated circuit inverts the data when among the eight data, five or more data are at a high level, and transmits the data to the data output buffers.
In order to perform the above-described operation, the semiconductor integrated circuit includes an apparatus for generating a DBI signal. As described above, the apparatus for generating a DBI signal determines the number of data that generate current, and generates a DBI signal. That is, when the DBI signal is enabled, a DBI control unit inverts the data that is transmitted to each of the data output buffers. On the other hand, when the DBI signal is disabled, the DBI control unit does not invert the data that is transmitted to each of the data output buffers. The DBI technique is applied to semiconductor integrated circuits, such as graphic processing units (GPUs), as well as to semiconductor memory apparatuses. The DBI technique can be implemented in general semiconductor integrated circuits that target low power consumption.
Hereinafter, an apparatus for generating a DBI signal according to the related art will be described as follows with reference to FIG. 1.
FIG. 1 is a block diagram showing the structure of an apparatus for generating a DBI signal in a semiconductor integrated circuit according to the related art. In FIG. 1, the apparatus for generating a DBI signal generates a DBI signal DBI_flag from eight data GIO<1:8> transmitted through global lines.
As shown in FIG. 1, the apparatus for generating a DBI signal includes four 2-input counters 2, two 6-input counters 4, and one 8-input counter 6. Each of the 2-input counters 2 receives two data among the eight data GIO<1:8> that are transmitted through the global input/output lines. Each of the 2-input counters 2 determines how many data are at a high level, that is, how many data have a logic value of ‘1’ between the two data, and enables a first 0-number determination signal dtng1<0>, a first 1-number determination signal dtng1<1>, or a first 2-number determination signal dtng1<2>. Then, using the two first 0-number determination signals dtng1<0>, the two first 1-number determination signals dtng1<1>, and the two first 2-number determination signals dtng1<2> that are transmitted from the two 2-input counters 2 among the four 2-input counters 2, each of the 6-input counters 4 determines how many data have the logic value of ‘1’ among the four data, and determines whether or not to enable a second 0-number determination signal dtng2<0>, a second 2-number determination signal dtng2<2>, a second 3-number determination signal dtng2<3>, and a second 4-number determination signal dtng2<4>. At this time, when among the four data, one data has a logic value of ‘1’, all of the second 0-number determination signal dtng2<0>, the second 2-number determination signal dtng2<2>, the second 3-number determination signal dtng2<3>, and the second 4-number determination signal dtng2<4> are disabled.
Then, using the two second 0-number determination signals dtng2<0>, the two second 2-number determination signals dtng2<2>, the two second 3-number determination signals dtng2<3>, and the two second 4-number determination signals dtng2<4> that are transmitted from the two 6-input counters 4, the 8-input counter 6 determines how many data have the logic value of ‘1’ among the eight data, and determines whether or not to enable the DBI signal DBI_flag. That is, the 8-input counter 6 enables the DBI signal DBI_flag when among the eight data, five or more data have the logic value of ‘1’, and disables the DBI signal DBI_flag when less than five data have the logic value of ‘1’ among the eight data.
As described above, since the apparatus for generating a DBI signal according to the related art includes the seven counters in order to perform an operation process including three steps, the area of the apparatus for generating a DBI signal is not small. Further, since the signal output lines of each of the 2-input counters are 1.5 times as many as the signal input lines, an improvement in integration of the apparatus for generating a DBI signal is limited. That is, the structure of the apparatus for generating a DBI signal according to the related art makes it difficult to increase an area margin.